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[VHDL-FPGA-Verilog] JEDEC

Description: DDR SDRAM的JEDEC标准，对DDR SDRAM的编程学习者有帮助。-The JEDEC standards for DDR SDRAM, DDR SDRAM programming for learners help.
Platform: | Size: 840704 | Author: 李娟 | Hits:

[VHDL-FPGA-Verilog] 61EDA_C2442

Description: ddr sdram控制器的例子，经过了仿真验证，没有问题-ddr sdram
Platform: | Size: 15360 | Author: liumeng | Hits:

[VHDL-FPGA-Verilog] sram

Description: sram操作vhdl源程序，内有sdram模型，控制器设计，及测试源程序-sram operating in vhdl \doc DDR SDRAM reference design documentation \model Contains the vhdl SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation Contains the vhdl testbench, modelsim project file, and library \source Contains the vhdl source files for the DDR SDRAM reference design \synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
Platform: | Size: 897024 | Author: chen | Hits:

[Linux-Unix] dramc

Description: 基于s3c6410的DDR SDRAM的裸板驱动源代码。-The DDR SDRAM based s3c6410 bare board driver source code.
Platform: | Size: 20480 | Author: use life to | Hits:

[VHDL-FPGA-Verilog] ddr_sdr

Description: DDR SDRAM 控制器 包含测试向量和仿真模型-DDR SDRAM control
Platform: | Size: 115712 | Author: 李晓翔 | Hits:

[VHDL-FPGA-Verilog] DATA-PATH.vhd

Description: signal data for ddr sdram
Platform: | Size: 2048 | Author: shiva | Hits:

[VHDL-FPGA-Verilog] Design-Of-DDR-SDRAM-Using-Verilog-HDL

Description: implementation of ddrsdram
Platform: | Size: 6144 | Author: steiner | Hits:

[VHDL-FPGA-Verilog] ddr_sdr_latest[1].tar

Description: ddr sdram 控制器的接口，为工业标准化存储设备提供简单的接口-The DDR SDRAM Controller provides the user with a simplified interface to industry standard memory devices. Using this controller makes accesses to DDR SDRAM devices as simple as possible.
Platform: | Size: 80896 | Author: hxr | Hits:

[Industry research] Datasheets

Description: Mobile DDR SDRAM MT46H32M16LF – 8 Meg x 16 x 4 banks MT46H16M32LF/LG – 4 Meg x 32 x 4 banks TFT-G240320LTSW-118W-E 16-megabit 2.5-volt or 2.7-volt DataFlash K9F1G08X0A S25FL032P S25FL032P Cover Sheet 32-Mbit CMOS 3.0 Volt Flash Memory
Platform: | Size: 7364608 | Author: Alak | Hits:

[Embeded Linux] MT46H32M16LF

Description: Mobile DDR SDRAM MT46H32M16LF – 8 Meg x 16 x 4 banks MT46H16M32LF/LG – 4 Meg x 32 x 4 banks
Platform: | Size: 2915328 | Author: Alak | Hits:

[Other] lpddr_verilog_model

Description: 美光 ddr sdram 仿真模型， 不可综合，用在测试平台模仿ddr sdram的功能。verilog语言编写。-Micron MOBILE DDR SDRAM simulation model. not synthesisable, used in tesetbench to emulation the function of ddr sdram. written in verilog
Platform: | Size: 39936 | Author: qiubin | Hits:

[Software Engineering] DDRSDRAM

Description: 基于VHDL的DDR SDRAM控制器的设计，实现数据的读写功能，迸发长度分为2，4，8-Based on the VHDL DDR SDRAM controller design, implementation of data read and write capabilities, burst into the length of 2, 4, 8
Platform: | Size: 823296 | Author: zhangjiefei | Hits:

[VHDL-FPGA-Verilog] dab1814114c3

Description: 此為採用ALTERA所做的DDR 控制器(verilog)- File/Directory Description ============================================================================= \doc DDR SDRAM reference design documentation \model Contains the verilog SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation Contains the verilog testbench, modelsim project file, and library \source Contains the verilog source files for the DDR SDRAM reference design \synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
Platform: | Size: 880640 | Author: 李志偉 | Hits:

[VHDL-FPGA-Verilog] sdram

Description: SDRAM 接口程序，里面涵盖 datasheet，原理容易懂，对学习ddr有兴趣的可以下来看看。-SDRAM interface program, which covers the datasheet, easy to understand the principle of learning ddr can look down.
Platform: | Size: 192512 | Author: 逍遥 | Hits:

[VHDL-FPGA-Verilog] DDRSDRAM_

Description: 基于FPGA 的DDR SDRAM 的重要资料 内附代码-FPGA-based DDR SDRAM code containing important information
Platform: | Size: 481280 | Author: 毕禹昕 | Hits:

[source in ebook] Chapter-9

Description: 9.1　异步FIFO设计实例　 9.2　DDR SDRAM Controller设计实例-9.1 Asynchronous FIFO design example 9.2 DDR SDRAM Controller Design Example
Platform: | Size: 3950592 | Author: shixiaodong | Hits:

[File Format] K4X2G323PC-8GC6(D8)_R09

Description: K4X2G323完整数据手册，三星DDR SDRAM芯片，128MB-K4X2G323 datasheet
Platform: | Size: 354304 | Author: 王文静 | Hits:

[Linux driver] sdram

Description: 基于ARM 的S3C6410 DDR内存的驱动，实现了内存的初始化等-The driver of DDR
Platform: | Size: 15360 | Author: 岳云 | Hits:

[Industry research] Design-and-implementation-of-High-Speed-Pipelined

Description: Design and implementation of High Speed Pipelined DDR SDRAM memory Controller
Platform: | Size: 772096 | Author: JAGRUTHI M S | Hits:

[Linux-Unix] atmel-sdramc

Description: Atmel (Multi-port DDR-)SDRAM Controller driver.
Platform: | Size: 1024 | Author: gtnieber | Hits:
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